Gallium arsenide (GaAs) devices have an advantage over silicon devices in speed and power consumption. The limiting factor for the extensive use of GaAs lies in the fact that it does not have a passivating layer and, therefore, devices such as GaAs MISFETs can not be satisfactorily produced, which limits the integration levels of GaAs integrated circuits. Compound semiconductor devices, such as FETs, HBTs, lasers, etc., need a properly passivated surface between electrodes for consistent device operation, improved device characteristics, and better reliability.
In GaAs MISFETs, for example, the gate-drain breakdown voltage is one of the most important factors limiting the maximum output power of the MISFET. Many prior methods to increase the breakdown voltage, such as a double gate recess and increased gate-drain spacing, are often accompanied by lower RF gain and/or drain saturation current. Attempts to increase the gate-drain breakdown voltage by placing an insulator between the gate metal and the MISFET channel, such as various nitrides and oxides, usually introduce undesirable interface states.
Recently, GaAs MISFETs with a low interface-state density were realized using a high-resistivity low-temperature-grown GaAs layer as the gate insulator. In a conventional gate MISFET, the high-resistivity low-temperature-grown GaAs layer is deposited and then etched to allow the deposition of source, drain and gate metal contacts. The major problem with this method is that a gap remains between the sides of the metal contacts and the high-resistivity low-temperature-grown GaAs layer, which substantially reduces the breakdown voltage of the MISFET. A typical example of such structures is disclosed in U.S. Pat. No. 5,041,393, entitled "Fabrication of GaAs Integrated Circuits" and issued Aug. 20, 1991.
In an attempt to solve this problem in the prior art, the gate metal was deposited so as to overlap the high-resistivity low-temperature-grown GaAs layer. However, the overlap gate process is difficult and complicated and requires a critical alignment and wet etching process and is not, therefore, easily manufacturable, especially for sub-micron gate dimensions.
Some attempts have been made at fluoridation of GaAs under F2 to produce a GaF.sub.3 /GaAs interface adjacent the surface of the substrate. The major problem with this procedure is that the GaF.sub.3 has a rhombohedral structure with a lattice mismatch of 8.02%. Also, F.sub.2 is very corrosive, which causes great reliability problems, and the interfacial region of the semiconductor device includes incompletely fluorinized gallium, arsenide, and free arsenide. Additionally, because of the lattice mismatch, the GaF.sub.3 has a relatively high interface state density (poor interface) and a very poor temperature stability, so that subsequent fabrication steps of annealing and the like are very detrimental to the GaF.sub.3.
It would be advantageous to have a fabrication method in which interelectrode areas of compound semiconductor devices are passivated so as to provide consistent device operation, improved device characteristics, and better reliability.
It is a purpose of the present invention to provide a new and improved method of fabricating semiconductor devices with a passivated surface area.
It is another purpose of the present invention to provide a new and improved method of fabricating semiconductor devices with a passivated surface area while providing consistent device operation, improved device characteristics, and better reliability.
It is still another purpose of the present invention to provide a new and improved method of fabricating semiconductor devices with a passivated surface area which is relatively easy and accurate to perform.
It is a further purpose of the present invention to provide new and improved semiconductor devices with passivated surface areas which substantially improve breakdown and reliability characteristics of the device.